1. Field of the Invention
This invention relates to a method of performing automatic test pattern generation for digital circuits, and design for testability, and also apparatuses for the method and design.
2. Description of the Prior Art
Automatic test pattern generation for sequential circuits involves a difficult problem, and even if an automatic test pattern generation program is used, it is generally difficult to obtain test patterns for all faults within a practical CPU time period. Furthermore, there ere also some faults which cause the automatic test pattern generation to abort. In order to solve these problems, scan path technique is widely used which makes it possible to write and read states externally by switching registers to a shift register configuration in the test mode. By making all of the registers scan registers, the test of a sequential circuit can be performed in three phases of: scan-in of the register state; partial testing of the combinational circuit; and scan-out of the register state, thereby allowing automatic test pattern generation problems to be handled as those of the combinational circuit. This enables automatic test pattern generation to be greatly simplified.
However, the structure for making all of the registers scan registers greatly increases the hardware overhead. Therefore, partial scan structure is used wherein only some of the registers have scan structure. In the partial scan, there is a high degree of freedom in selecting which registers are to be scan structure, and there have been proposed several methods of selecting registers which should be changed to scan registers.
Techniques of partial scan design are taught in "A Complete Solution to the Partial Scan Problem" (Int. Test Conf., pp. 44-51, 1987) and the references cited therein.
When considered from the standpoint of scan register selection, the prior art techniques can be generally classified into two categories shown in FIGS. 9A and 9B. In the method shown in FIG. 9A, the causes for low fault coverage are investigated after performing automatic test pattern generation, and then questioned registers are changed to scan registers. In the method shown in FIG. 9B, before performing automatic test pattern generation, registers which will likely present problems in test pattern generation are estimated based on the circuit topology, and then these registers are changed to scan registers.
The former method requires great amounts of the CPU time and memory capacity. The later method does not guarantee that registers which present problems in test pattern generation will actually be scanned, so that it is difficult to obtain high fault coverage with small area overhead.